On Determining Polynomial Evaluation Structures for FPGA based Custom Computing Machines

In this paper we identify and present techniques for determining and constructing parallel evaluation structures for polynomials on Custom Computing Machines (CCMs). Since CCMs achieve high throughput rates by the eeective use of pipelining, our primary interest is of the construction of resource eecient structures for any given polynomial P(x). Speciically, we consider CCMs whose conngurable logic resource exists as a set of Field Programmable Gate Arrays (FPGAs). We target our polynomial structure implementations for FPGAs and show how to construct them conscious of area requirements. Compared to known evaluation techniques for traditionally known parallel processing paradigms, our results are justiied for providing low area parallel evaluation structures on CCMs.